In recent years, research has been conducted on a processor including computing elements forming a double torus structure. The computing elements forming a double torus structure are M×N computing elements configured such that M (M is an integer of 1 or more) computing elements arranged in the row direction and N (N is an integer of 1 or more) computing elements arranged in the column direction are connected to each other in a torus-like manner, for example.
In the processor including the computing elements as above, the frequency of accessing a memory (for example, a dynamic random access memory (DRAM)) during processing is reduced by performing the processing while sharing data stored in registers of the computing elements among the plurality of computing elements. As a result, the processor as described above can realize high-speed processing (for example, see Japanese Laid-open Patent Publication No. H06-175986).